USRE23699E - Pulse delay circuit - Google Patents

Pulse delay circuit Download PDF

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Publication number
USRE23699E
USRE23699E US23699DE USRE23699E US RE23699 E USRE23699 E US RE23699E US 23699D E US23699D E US 23699DE US RE23699 E USRE23699 E US RE23699E
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Prior art keywords
potential
anode
pulse
junction
positive
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/145—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of resonant circuits

Definitions

  • This invention relates to pulse delay circuit arrangements, and more particularly to improvements over the delay circuit disclosed and claimed in copending application Serial No. 262,732, filed December 21, 1951 as a division of application Serial No. 47,626 of Byron L. Havens, filed September 3, 1948, and assigned to the same assisneeas the present application.
  • Pulse delay circuit arrangements of the type herein contemplated are particularly useful where the input signal comprises a coded pulse train in which the pulses occur during uniform time intervals, and'where it is desired to shift each such pulse into a subsequent time interval. Pulse delay circuits of this type are especially useful. for example, in electronic computers, in which the input signal comprises a series of pulses representing binary digits.
  • Another object of the present invention is to provide a pulse delay circuit arrangement which does notplace stringent requirements regarding impedance, wave shape or uniformity of magnitude on the signal and synchronizing pulse sources.
  • An additional object of the present invention is to provide a pulse delay circuit arrangement which can receive a second input pulse while producing an output pulse corresponding to a first input pulse, without interaction therebetween.
  • Still another object of the present invention is to provide a pulse delay circuit arrangement which furnishes an output pulse having a readily usable waveform.
  • a pulse delay circuit arrangement which comprises a combination of components including first and second input terminals [means for developing] for applying a positivegoing pulse to the control electrode of an electron discharge device when positive pulses are applied to both of the input terminals. and an electron discharge device having a control electrode, a
  • Means are provided for applying a positive-going pulse to the control electrode.
  • positive and negative potential sources having a common terminal,
  • a series network comprising a plurality of impedance elements is connected between the anode and the negative potential source, the Junction of a pair of these impedance elements being connected to the junction of a first pair of the rectifier elements.
  • An output terminal is connected to the junction of a second pair of rectifier elements.
  • the means for developing a positive-going pulse when positive pulses are applied to both of the input terminals comprises rectifiers connected in series respectively with the two input terminals, these rectifiers are [preferably being] arranged to offer minimum resistance to current flow toward the input terminals.
  • This portion of the circuit may be referred to as an and circuit.
  • the clamping potential may have a predetermined phase relationship with respect to the pulse applied to one of the input terminals.
  • Such pulses may be designated synchronizing pulses and may occur periodically at uniformly spaced intervals corresponding with the time intervals of the pulse train applied to the signal input terminal.
  • Fig. 1 is a schematic circuit diagram of a pulse delay circuit arrangement in accordance with a preferred embodiment of the present invention.
  • Fig. 2 is a graphical representation, to a common time base, of the approximate waveforms which exist in various portions of the system of Fig. 1, these portions being designated by the encircled reference numerals.
  • Fig. 1 of the drawing there are shown input terminals Ill and II, to which are applied respectively input signal pulses (curve I) and synchronizing pulses (curve 2).
  • input signal pulses curve I
  • synchronizing pulses curve 2
  • rectifiers l2 and I3 connected respectively between a Junction i4 and input terminals l0 and II, and [preferably] arranged so that they ofier minimum resistance to current flow toward these input terminals.
  • a resistor I! is connected between Junction l4 and the left-hand control electrode lli of an electron discharge device l1, which is shown as a [preferably of the] dual triode. [type.] Lefthand cathode l8 of discharge device I1 is grounded, and left-hand anode ll of discharge device I1 is connected through a load impedance comprising an inductor 2
  • a series network comprising a plurality of rectifier elements 25, 23 and 21 connected between negative potential terminal 23 and, through a resistor 29, a source of clamping potential 33.
  • the waveform of this potential is indicated by curve 4 (Fig. 2).
  • Rectifier elements 25, 26 and 21 are [preferably] arranged to oifer minimum resistance to current flow fromnegative potential terminal 23 to clamping potential source 33.
  • a series network comprising a plurality of impedance elements including capacitor 3
  • junction 35 between rectifier elements 26 and 21 may be connected to an output terminal 43 of the delay circuit arrangement itself.
  • a series network comprising resistor 36 and capacitor 31 is connected between right-hand control electrode 33 of discharge device l1 and ground, the junction between impedance elements 38 and 31 being connected to junction 35.
  • Right-hand anode 33 of discharge device I1 is connected to positive potential terminal 23
  • right-hand cathode 40 of discharge device I1 is connected through an impedance element or resistor 4
  • Resistors II and 36 serve to prevent any parasitic oscillations which might otherwise occur.
  • junction I4 becomes positive to thereby provide an input to the control grid 16 and the left-hand portion of discharge device I1 be-- comes conductive.
  • the positivegoing edge of the pulse (curve 3) at anode I9 causes a positive-going pulse to pass through capacitor 3
  • Resistor 29 1,200 ohms.
  • Rectifiers i2, Ii, 25, 28- Type 1N45 Rectifiers i2, Ii, 25, 28- Type 1N45.
  • Type IZAV'I Potential terminal 23.... +150 volts. Potential terminal 28"-- --30 volts. Potential terminal 1L--- -82 volts.
  • a pulse delay circuit arrangement comprising the combination of: first and second input terminals; means for developing a positivegoing pulse when positive pulses are applied to both said input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positivegoing pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; a series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential; a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the junction of a first pair of said rectifier elements; and an output terminal connected to the junction of a second pair of said rectifier elements.
  • a pulse delay circuit arrangement comprising the combination of: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals, said means comprising first and second rectifiers connected respectively in series with said first and second input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positive-going pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; 9.
  • series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential; a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the junction of a, first pair of said rectifier elements; and an output terminal connected to the junction of a second pair of said rectifier elements.
  • a pulse delay circuit arrangement comprising the combination oi: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals, said means comprising first and second rectifiers connected respectively in series with said first and second input terminals and offering minimum resistance to current fiow toward said input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positive-going pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; 3, series network comprising a plurality oi.
  • rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential;'a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the junction of a first pair of said rectifier elements; and an output terminal connected to the junction of a second pair of said rectifier elements.
  • a pulse delay circuit arrangement comprising the' combination of: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positive-going pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; a series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential, said clamping potential having a predetermined phase relationship to the positive pulses applied to one of said input terminals; a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the Junction of a first pair of said rectif
  • a pulse delay circuit arrangement comprising the combination of: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positivegoing pulse to said control electrode; a load impedance having a reactive component connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; a series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a.
  • a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the junction of a first pair of said rectifier elements; and an output terminal connected to the junction of a second pair of said rectifier elements.
  • a pulse delay circuit arrangement comprising the combination of: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals; an electron discharge device having a control electrode, a cathode and an anode; means for applying said positive-going pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; a series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential; a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, one of said impedance elements being capacitively reactive and the junction of said impedance elements being connected to the junction of a first pair of said rectifier elements; and an output terminal connected to the junction of
  • a pulse delay circuit arrangement comprising the combination of: first and second input terminals; means for developing a positive-going pulse when positive pulses are applied to both said input terminals; an electron discharge de vice having a control electrode, a cathode and an anode; means for applying said positive-going pulse to said control electrode; a load impedance connected between said anode and a source of anode potential; means for supplying said cathode with a potential negative with respect to said anode potential; a series network comprising a plurality of rectifier elements connected at one end to a potential negative with respect to said anode potential and at the other end to a source of clamping potential, said rectifier elements offering minimum resistance to current flow toward said source of clamping potential; a series network comprising a pair of impedance elements connected at one end to said anode and at the other end to a potential negative with respect to said anode potential, the junction of said impedance elements being connected to the junction of a first pair of said rectifier elements; and
  • a pulse delay circuit arrangement comprising the combination of: a first electron discharge device having a control electrode; a cathode and an anode; an input terminal connected to said control electrode; positive and negative potential sources having a common terminal, said common terminal being connected to said cathode and said negative potential source having taps thereon; a load impedance connected between said anode and said positive potential source; a series network comprising first, second and third rectifier elements connected between a tap on said negative potential source and a source of clamping potential; a series network comprising first and second impedance elements connected between said anode and a tap on said negative potential source.
  • the junction of said first and second impedance elements being connected to the junction of said first and second rectifier elements; a second electron discharge device having a control eletrode, a cathode and an anode, said anode being connected to said positive potential source; a series network comprising third and fourth impedance elements connected between said last-mentioned control electrode and said common terminal. the junction of said third and fourth impedance elements being. connected to the junction of said second and third rectifier elements; a fifth impedance element connected between said lastmentioned cathode and a tap on said negative potential source; and an output terminal connected to said last-mentioned cathode.
  • a pulse delay circuit arrangement comprising'the combination of: a first electron discharge device having a control electrode, a cathode and an anode; an input terminal connected to said control electrode; positive and negative potential sources having a common terminal, said common terminal being connected to said cathode and said negative potential source having taps thereon; a load impedance having a reactive component connected between said anode and said positive potential source; a series network comprising first, second and third rectifier elements connected between a tap on said negative potential source and a source of clamping potential; a series network comprising first and second impedance elements connected between said anode and a tap on said negative potential source, the junction of said first and second impedance elements being connected to the junction of said first and second rectifier elements; a second electron discharge device having a control electrode, a cathode and an anode, said anode being connected to said positive potential source; a series network comprising third and fourth impedance elements connected between said lastmentioned control electrode and said common terminal, the junction
  • a pulse delay circuit arrangement comprising the combination of: a first electron discharge device having a control electrode, a cathode and an anode; an input terminal connected to said control electrode; positive and negative potential sources having a common terminal, said common terminal being connected to said cathode and said negative potential source having taps thereon; a load impedance connected between said anode and said positive potential source; a series network comprising first, second and third rectifier elements connected between a tap on said negative potential source and a source of clamping potential; a series network comprising first and second impedance elements connected between said anode and a tap on said negative potential source, said first impedance element being capacitively reactive and the junction of said first and second impedance elements being connected to the junction of said first and second rectifier elements; a second electron discharge device having a control electrode, a cathode and an anode, said anode being connected to said positivepotential source; a series network comprising third and fourth impedance elements connected between said last-mentioned control
  • first and second impedance elements being connected to the junction of said connected between said to said control electrode; positive and negativepotential sources having a common terminal, said common terminal being connected to said cathode and said negative potential source having a load impedance connected between said anode and said positive potential source; a series network comprising first, second and third rectifier elements connected between a tap on said negative potential source and a source-oi clamping potential, said rectifier elements oflering minimum resistance to current flow from said negative potential source to said sourceoi clamping potential; a series network comprising flrstand second impedance elements connected between said anode and a tap on said the junction of said first and second rectifier elements; a second electron discharge device having a control electrode, a cathode and an anode, said anode being connected to said positive potential source; a series network comprising third and fourth impedance elements last-mentioned control electrode and said common terminal, the junction of said third and fourth impedance elements being connected to the junction o
  • a d vice for receiving an input and providing an output simultaneously; an output terminal; input means including an and circuit for receiving a series of electrical manifestations, each occurring within a predetermined time interval; delay circuit means ioining said input means and said output terminal for utilizing each said electrical manifestation to produce an elec- 1o trical manifestation at said output terminal during the next succeeding time interval after said predetermined time interval, said means including a grid controlled cathode follower tube having its cathode connected to said output terminal and its control grid connected through a capacitor to ground.
  • a pulse delay circuit comprising; a discharge. device including a control electrode, a cathode and an anode, and first potential means for applying predetermined potentials thereto; "and circuit means for applying an input pulse to be delayed to said control electrode to render said device operable; series connected rectifiers joining a second potential source less positive than the potential applied to said anode and a source of clamping potential having a predetermined phase relationship to said input pulses; series connected elements ioining said anode to a third source of potential less positive than. said second source, a junction of said elements being connected to a junction of said rectiflers; and a capacitor connected to another function of said rectiflers to produce a pulse at a predetermined time after occurrence of said input pulse.
  • the invention set forth in claim 13 including an output cathode follower having an input and an output terminal and a connection from the last-mentioned iunction of said rectifiers to the input terminal thereof.
  • an "and circuit for applying an input pulse to said circuit when .two pulses are applied simultaneously thereto a first grid controlled tube connected to be operable to produce an output in response to each said input pulse; a second grid controlled tube operable as a cathode follower and having an output terminal connected to'the cathode thereof and a capacitor coupling the control grid thereof to ground; and unidirectional current flow means connecting the control grid of said second tube to the output of said first tube.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)
  • Generation Of Surge Voltage And Current (AREA)
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US23699D 1951-07-30 Pulse delay circuit Expired USRE23699E (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US302607XA 1951-07-30 1951-07-30

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USRE23699E true USRE23699E (en) 1953-08-18

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US23699D Expired USRE23699E (en) 1951-07-30 Pulse delay circuit

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US (1) USRE23699E (en])
BE (1) BE512482A (en])
CH (1) CH302607A (en])
DE (1) DE1026785B (en])
FR (1) FR1074558A (en])
GB (1) GB719418A (en])

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2974866A (en) * 1954-03-30 1961-03-14 Ibm Electronic data processing machine
US3467838A (en) * 1964-09-03 1969-09-16 English Electric Computers Ltd Electric pulse delay circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE443144A (en]) * 1940-10-25
CH236114A (de) * 1942-01-19 1945-01-15 Skoda Kp Einrichtung zum Sperren elektrischer Kreise.
BE479412A (en]) * 1944-08-07
US2512152A (en) * 1945-09-14 1950-06-20 Us Sec War Pulse delay circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2974866A (en) * 1954-03-30 1961-03-14 Ibm Electronic data processing machine
US3467838A (en) * 1964-09-03 1969-09-16 English Electric Computers Ltd Electric pulse delay circuit

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FR1074558A (fr) 1954-10-06
GB719418A (en) 1954-12-01
BE512482A (en])
CH302607A (fr) 1954-10-31
DE1026785B (de) 1958-03-27

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